2015-2016 The list of papers selected for presentation  the following:

Papers in red have already been taken

Paper Source
A million spiking-neuron integrated circuit with a scalable communication network and interface.
P. Merolla et al.. Science 8 August 2014: Vol. 345 no. 6197 pp. 668-673 		[pdf]
Biologically-Inspired Massively-Parallel Architectures - computing beyond a million processors,
S.B. Furber and A.D. Brown, Proc. 9th International Conference on the Application of Concurrency to System Design (ACSD'09) 		[pdf]
Composite Cores: Pushing Heterogeneity into a Core.
A. Lukefahret al.. MICRO 2012 		[pdf]
Thin servers with smart pipes: designing SoC accelerators for memcached.
K. Lim et al. ISCA 2013		 [pdf]
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators.
Y. Lee, et al., ACM TOCS 2013
[pdf]
Efficient Digital Neurons for Large Scale Cortical Architectures.
James E. Smith . ISCA 2014		 [pdf]
A reconfigurable fabric for accelerating large-scale datacenter services.
A. Putnam et al. ISCA 2014		 [pdf]
The CHERI capability model: Revisiting RISC in an age of risk,
J.Woodruff et al. ISCA 2014		 [pdf]
Race Logic: A Hardware Acceleration for Dynamic Programming Algorithms. A. Madhavan et al. ISCA 14 [pdf]
BigDataBench: a Big Data Benchmark Suite from Internet Services.
Lei Wang et al. HPCA 14		 [pdf]
3D Stacking of High-Performance Processors.
P. Emma et al. HPCA 14 		[pdf]
The Netflix Challenge: Datacenter Edition,
C. Delimitrou et al. ,CAL January-June 2013 (vol. 12 no. 1), pp. 29-32  		[pdf]
Quality-Programmable Vector Processors for Approximate Computing
S. Venkataramani et al. MICRO 2013 		[pdf]
SAGE: Self-Tuning Approximation for Graphics Engines
M. Samadi et al. MICRO 2013  		[pdf]
Use It Or Lose It: Wear-out and Lifetime in Future Chip Multiprocessors
H. Kim et al. MICRO 2013		 [pdf]
Any other you want, make proposal to your professor.  

 

FINAL 2013/2014 COURSE ASSIGNMENTS (Pick one)

Name Due Date Docs
FINAL PROJECT - Extensions to the processor (one of the following)
   1) Bonus parts from Lab10 document
   2) Direct mapped cache
   3) Branch predictor
   4) Fine Grain Multithreading

 24/01
  
Total Cost of Ownership

Optimizing Data-Center TCO with Scale-Out Processors,; B. Grot, D. Hardy, P. Lofti-Kamran, B. Falsafi, C. Nicopoulos, Y. Sazeides; IEEE MICRO Sept-Oct 2012 		  [pdf]
Neuromorphic Accelerators

"Implementation of signal processing tasks on neuromorphic hardware"; Temam, O.; Heliot, R., The 2011 International Joint Conference on Neural Networks (IJCNN), pp.1120,1125, July 31 2011-Aug. 5 2011

"A reconfigurable accelerator for neuromorphic object recognition" Sabarad, J.; Kestur, S.; Mi Sun Park; Dantara, D.; Narayanan, V.; Yang Chen; Khosla, D.,  2012 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.813,818, Jan. 30 2012-Feb. 2 2012 		  [pdf]



[pdf]
FPGA accelerator boards and markets
General description of use cases, companies/products, speed-ups reported.		    
FPGA accelerator research
(Some examples:)
Evaluating FPGA-acceleration for real-time unstructured search, Chalamalasetti, S.; Margala, M.; Vanderbauwhede, W.; Wright, M.; Ranganathan, P., 2012 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp.200,209, 1-3 April 2012

"Accelerating Millions of Short Reads Mapping on a Heterogeneous Architecture with FPGA Accelerator"; Wen Tang; Wendi Wang; Bo Duan; Chunming Zhang; Guangming Tan; Peiheng Zhang; Ninghui Sun,  IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2012 pp.184,187, April 29 2012-May 1 2012 		  [pdf]



[pdf]
New languages in circuit design

Present languages such as SystemC, Chisel, MyHDL. Pros and Cons.
    
Wearable Architectures and CPUs

Present the efforts undertaken by different manufacturers. Concentrate possibly on smartwatches. Describe components, energy requirements, and performance. Describe the CPUs used and compare them (include Intel Quark in the comparison)