Interesting papers to present (Q2 2018/2019) :

# Paper Title
1 Error Correlation Prediction in Lockstep Processors for Safety-critical Systems. MICRO 2018
2 Adaptive Voltage/Frequency Scaling and Core Allocation for Balanced Energy and Performance on Multicore CPUs. HPCA 2019
3 Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBIST. HPCA 2019
4 Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures. HPCA 2018
5 Power and Energy Characterization of an Open Source 25-core Manycore Processor. HPCA 2018
6 Computing in memory with FeFETs. ISLPED 2018
7 Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM based Last Level Cache. ISCA 2018
8 Enabling Scientific Computing on Memristive Accelerators. ISCA 2018
9 A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic. ISLPED 2017
10 Battery Assignment and Scheduling for Drone Delivery Businesses. ISLPED 2017
11 Harnessing Voltage Margins for Energy Efficiency in Multicore CPUs. MICRO 2017
12 An Experimental Microarchitecture for a Superconducting Quantum Processor. MICRO 2017
13 Very Low Voltage (VLV) Design. ICCD 2017
14 Exploring and Analyzing the Real Impact of Modern On-Package Memory on HPC Scientific Kernels. SC 2017
15 Experimental and Analytical Study of Xeon Phi Reliability. SC 2017
16 Failure Detection and Propagation in HPC systems. SC 2016
17 Unprotected Computing: A Large-Scale Study of DRAM Raw Error Rate on a Supercomputer. SC 2016
9999 Project or Lab 5

Interesting papers to present : (as of Q2 2017/2018)

1 PM3: Power Modeling and Power Management for Processing-in-Memory. HPCA 2018
2 Sensing CPU voltage noise through Electromagnetic Emanations. CAL 2017.
3 Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures. HPCA 2018
4 Power and Energy Characterization of an Open Source 25-core Manycore Processor. HPCA 2018
5 A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic. ISLPED 2017
6 Battery Assignment and Scheduling for Drone Delivery Businesses. ISLPED 2017
7 Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content. MICRO 2017
8 Harnessing Voltage Margins for Energy Efficiency in Multicore CPUs. MICRO 2017
9 Architectural Tradeoffs for Biodegradable Computing. MICRO 2017
10 An Experimental Microarchitecture for a Superconducting Quantum Processor. MICRO 2017
11 Neural Trojans. ICCD 2017
12 Very Low Voltage (VLV) Design. ICCD 2017
14 Exploring and Analyzing the Real Impact of Modern On-Package Memory on HPC Scientific Kernels. SC 2017
15 Experimental and Analytical Study of Xeon Phi Reliability. SC 2017
16 DICE: Compressing DRAM Caches for Bandwidth and Capacity. ISCA 2017
17 Failure Detection and Propagation in HPC systems. SC 2016
18 Unprotected Computing: A Large-Scale Study of DRAM Raw Error Rate on a Supercomputer. SC 2016

Interesting papers to present (as of Q1 2015/2016):

DATE'15 Energy-Efficient Cache Design in Emerging Mobile Platforms: The Implications and Optimizations Kaige Yan and Xin Fu, University of Houston, US  
DATE'15 Soft-Error Reliability and Power Co-optimization for GPGPUs Register File Using Resistive Memory Jingweijia Tan, Zhi Li and Xin Fu University of Houston, US;University of Kansas, US  
HPCA'15 Quantifying sources of error in McPAT and potential impacts on architectural studies. Sam Likun Xi; Jacobson, H.; Bose, P.; Gu-Yeon Wei; Brooks, D  
ISLPED'14 Energy characterization and instruction-level energy model of Intel's Xeon Phi processor Shao, Y.S.; Brooks, D  
Sustainable Computing A survey of architectural techniques for improving cache power efficiency Sparsh Mittal  
ISCA'13 Convolution Engine: Balancing Efficiency and Flexibility in Specialized Computing Wajahat Qadeer, Rehan Hameed, Ofer Shacham, Preethi Venkatesan, Christos Kozyrakis, Mark Horowitz, Stanford University  
DSN'05 Microprocessor Sensitivitity to Failures: Control vs. Execution and Combinational vs. Sequential Logic Giacinto Paolo Saggese, Anoop Vetteth, Zbigniew Kalbarczyk, Ravishankar Iyer  
ICCD'14 Boolean circuit design using emerging tunnel devices Sedighi, B.; Nahas, J.J.; Niemier, M.; Hu, X.S  
HPCA'15 Understanding GPU Errors on Large-scale HPC Systems and the Implications for System Design and Operation Tiwari, D.; Gupta, S.; Rogers, J.; Maxwell, D.; Rech, P.; Vazhkudai, S.; Oliveira, D.; Londo, D.; DeBardeleben, N.; Navaux, P.; Carro, L.; Bland, A  
MICRO'13 Kiln: Closing the Performance Gap Between Systems With and Without Persistence Support Jishen Zhao (Pennsylvania State University), Sheng Li (Hewlett-Packard Labs), Doe Hyun Yoon (IBM Thomas J. Watson Research Center), Yuan Xie (Pennsylvania State University/AMD Research), and Norman P. Jouppi (Google)  
MICRO'14 DaDianNao: A Machine-Learning Supercomputer Yunji Chen; Tao Luo; Shaoli Liu; Shijin Zhang; Liqiang He; Jia Wang; Ling Li; Tianshi Chen; Zhiwei Xu; Ninghui Sun; Temam, O  
SC'14 Application Centric Energy-Efficiency Study of Distributed Multi-Core and Hybrid CPU-GPU Systems Cumming, B.; Fourestey, G.; Fuhrer, O.; Gysi, T.; Fatica, M.; Schulthess, T.C.  

Interesting papers to present (as of Q2 2014/2015):

HPCA'15 Quantifying sources of error in McPAT and potential impacts on architectural studies. Sam Likun Xi; Jacobson, H.; Bose, P.; Gu-Yeon Wei; Brooks, D  
SC'13 Feng Shui of Supercomputer Memory: Positional Effects in DRAM and SRAM Faults  Vilas Sridharan (Advanced Micro Devices, Inc.), Jon Stearley (Sandia National Laboratories), Nathan DeBardeleben, Sean Blanchard (Los Alamos National Laboratory), Sudhanva Gurumurthi (Advanced Micro Devices, Inc.) 4/6
ISLPED'14 Energy characterization and instruction-level energy model of Intel's Xeon Phi processor Shao, Y.S.; Brooks, D  
Sustainable Computing A survey of architectural techniques for improving cache power efficiency Sparsh Mittal  
ISCA'13 Convolution Engine: Balancing Efficiency and Flexibility in Specialized Computing Wajahat Qadeer, Rehan Hameed, Ofer Shacham, Preethi Venkatesan, Christos Kozyrakis, Mark Horowitz, Stanford University  
DSN'05 Microprocessor Sensitivitity to Failures: Control vs. Execution and Combinational vs. Sequential Logic Giacinto Paolo Saggese, Anoop Vetteth, Zbigniew Kalbarczyk, Ravishankar Iyer  
ICCD'14 Boolean circuit design using emerging tunnel devices Sedighi, B.; Nahas, J.J.; Niemier, M.; Hu, X.S  
HPCA'15 Understanding GPU Errors on Large-scale HPC Systems and the Implications for System Design and Operation Tiwari, D.; Gupta, S.; Rogers, J.; Maxwell, D.; Rech, P.; Vazhkudai, S.; Oliveira, D.; Londo, D.; DeBardeleben, N.; Navaux, P.; Carro, L.; Bland, A  
HPCA'15 High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches Jaleel, A.; Nuzman, J.; Moga, A.; Steely, S.C.; Emer, J. 4/6
MICRO'13 Kiln: Closing the Performance Gap Between Systems With and Without Persistence Support Jishen Zhao (Pennsylvania State University), Sheng Li (Hewlett-Packard Labs), Doe Hyun Yoon (IBM Thomas J. Watson Research Center), Yuan Xie (Pennsylvania State University/AMD Research), and Norman P. Jouppi (Google)  
MICRO'14 DaDianNao: A Machine-Learning Supercomputer Yunji Chen; Tao Luo; Shaoli Liu; Shijin Zhang; Liqiang He; Jia Wang; Ling Li; Tianshi Chen; Zhiwei Xu; Ninghui Sun; Temam, O  
SC'14 Scaling the Power Wall: A Path to Exascale Villa, O.; Johnson, D.R.; Oconnor, M.; Bolotin, E.; Nellans, D.; Luitjens, J.; Sakharnykh, N.; Peng Wang; Micikevicius, P.; Scudiero, A.; Keckler, S.W.; Dally, W.J. 4/6
SC'14 Application Centric Energy-Efficiency Study of Distributed Multi-Core and Hybrid CPU-GPU Systems Cumming, B.; Fourestey, G.; Fuhrer, O.; Gysi, T.; Fatica, M.; Schulthess, T.C.  

 

 

Interesting papers to present (as of Q2 2013/2014):

SC'13 A 'cool' way of improving the reliability of HPC machines Osman Sarood, Esteban Meneses, Laxmikant V. Kale (UIUC)  
SC'13 Feng Shui of Supercomputer Memory: Positional Effects in DRAM and SRAM Faults  Vilas Sridharan (Advanced Micro Devices, Inc.), Jon Stearley (Sandia National Laboratories), Nathan DeBardeleben, Sean Blanchard (Los Alamos National Laboratory), Sudhanva Gurumurthi (Advanced Micro Devices, Inc.)  
HPCA'141 Understanding the Impact of Gate-Level Physical Reliability Effects on Whole Program Execution Raghuraman Balasubramanian (University of Wisconsin-Madison), Karthikeyan Sankaralingam (University of Wisconsin-Madison) 4/6
HPCA'141 3D Stacking of High-Performance Processors Philip Emma, Alper Buyuktosunoglu, Michael Healy, Krishnan Kailas, Valentin Puente, Roy Yu, Allan Hartstein, Pradip Bose, Jaime Moreno (IBM) 28/5
ISCA'13 Continuous Real-World Inputs Can Open Up Alternative Accelerator Designs Bilel Belhadj, CEA Antoine Joubert, CEA Zheng Li, INRIA Rodolphe Heliot, CEA Olivier Temam, INRIA 29/5
ISCA'13 Convolution Engine: Balancing Efficiency and Flexibility in Specialized Computing Wajahat Qadeer, Rehan Hameed, Ofer Shacham, Preethi Venkatesan, Christos Kozyrakis, Mark Horowitz, Stanford University  
ISCA'13 An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms Jamie Liu, Carnegie Mellon University Ben Jaiyen, Carnegie Mellon University Yoongu Kim, Carnegie Mellon University Chris Wilkerson, Intel Corporation Onur Mutlu, Carnegie Mellon University 4/6
ISCA'13 Quantum Rotations: A Case Study in Static and Dynamic Machine-Code Generation for Quantum Computers  Daniel Kudrow, UC Santa Barbara Kenneth Bier, UC Santa Barbara Zhaoxia Deng, UC Santa Barbara Diana Franklin, UC Santa Barbara Yu Tomita, Georgia Institute of Technology Kenneth Brown, Georgia Institute of Technology Frederic Chong, UC Santa Barbara 29/5
ISCA'13 Resilient Die-stacked DRAM Caches   Jaewoong Sim, Georgia Institute of Technology  Gabriel H. Loh, AMD  Vilas Sridharan, AMD  Mike O'Connor, AMD 4/6
PACT'13 Coordinated Power-Performance Optimization in Manycores      Hiroshi Sasaki, Satoshi Imamura, Koji Inoue (Kyushu University) 29/5
MICRO'13 Kiln: Closing the Performance Gap Between Systems With and Without Persistence Support Jishen Zhao (Pennsylvania State University), Sheng Li (Hewlett-Packard Labs), Doe Hyun Yoon (IBM Thomas J. Watson Research Center), Yuan Xie (Pennsylvania State University/AMD Research), and Norman P. Jouppi (Google)  
MICRO'13 Heterogeneous System Coherence for Integrated CPU-GPU Systems Jason Power, Arkaprava Basu (University of Wisconsin-Madison). Junli Gu, Sooraj Puthoor, Bradford M. Beckmann (AMD), Mark D. Hill (University of Wisconsin-Madison, AMD), Steven K. Reinhardt (AMD), and David A. Wood (University of Wisconsin-Madison, AMD) 28/5
MICRO'13 Use It Or Lose It: Wear-out and Lifetime in Future Chip Multiprocessors Hyungjun Kim (Texas A&M University), Arseniy Vitkovskiy (Cyprus University of Technology), Paul V. Gratz (Texas A&M University), and Vassos Soteriou (Cyprus University of Technology) 28/5

1This conference is very recent. Email me to get the proceedings as they are not yet available online.

Interesting papers to present : (as of Q2 2009/2010)

1 ISCA 2009 Hybrid Cache Architecture with Disparate Memory Technologies
Xiaoxia Wu (The Pennsylvania State University), Jian Li, Lixin Zhang, Evan Speight, Ram Rajamony (IBM Austin Research Laboratory), Yuan Xie (The Pennsylvania State University)
2 MICRO 2009

Tribeca: Design for PVT Variations with Local Recovery and Fine-grained Adaptation
Meeta Sharma Gupta, Harvard University; Jude A. Rivers, Pradip Bose, IBM; Gu-Yeon Wei, David Brooks, Harvard University
3 MICRO 2009 
Improving Cache Lifetime Reliability at Ultra-low Voltages 
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu, Intel
4 MICRO 2009 
Characterizing Flash Memory: Anomalies, Observations, and Applications 
Laura M.Grupp, Adrian M. Caulfield, Joel Coburn, Steven Swanson, Eitan Yaakobi, Paul H. Siegel, Jack K. Wolf, 
University of California, San Diego
5 HPCA 2010 
A Hybrid Solid-State Storage Architecture for Performance, Energy Consumption and Lifetime Improvement
Guangyu Sun, Yongsoo Joo, Yibo Chen, Yuan Xie, Pennsylvania State University
Yiran Chen, Helen Li, Seagate
6 HPCA 2010 
Worth their Watts? An Empirical Study of Datacenter Servers
Arunchandar Vasan, Anand Sivasubramaniam, Vikrant Shimpi, T. Sivabalan, Rajesh Subbiah, Tata Consultancy Services
7 HPCA 2010 
Architecting for Power Management: The POWER7 Approach
Malcolm Ware, Karthick Rajamani, Michael Floyd, Bishop Brock, Juan C. Rubio, Freeman Rawson, John B. Carter, IBM
8 ISMME 2003 A vision of energy aware computing from chips to data centers
Chandrakant D. Patel, HP

 

 

Interesting papers to present : (as of Q2 2008/2009)

1 HPCA 2009

C-Oracle: Predictive Thermal Management for Data Centers
Luiz Ramos, Rutgers University, Ricardo Bianchini, Rutgers University;
2 HPCA 2010

Variation-Aware Dynamic Voltage/Frequency Scaling

Sebastian Hebert, Diana Marculescu, Carnegie Mellon University

3 HPCA 2009 
Prediction of CPU Idle-Busy Activity Pattern 
Qian Diao and Justin J Song (Intel Corporation)
4 HPCA 2010 
A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs
 Guangyu Sun, Xiangyu Dong, Yuan Xie, Penn State University
Jian Li, IBM;Yiran Chen, Seagate Tech
5 HPCA 2009 
Performance and Power Optimization through Data Compression in Network-on-Chip Architectures
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulus, Dongkook Park, Vijay Narayanan, Pennsylvania State University;
Ravishankar Iyer, Mazin S. Yousif, Intel Corporation; Chita R Das, Pennsylvania State University;
6 ISCA 2008 
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments
Kevin Lim, Parthasarathy Ranganathan, Jichuan Chang, Chandrakant Patel, Trevor Mudge, and Steven Reinhardt
7 ISCA 2008

3D-Stacked Memory Architectures for Multi-Core Processors
Gabriel H. Loh

 

Interesting papers to present : (as of Q2 2007/2008)

1 HPCA 2009

C-Oracle: Predictive Thermal Management for Data Centers
Luiz Ramos, Rutgers University, Ricardo Bianchini, Rutgers University;
2 HPCA 2009

 System Level Analysis of Fast, Per-Core DVFS using On-Chip Switching Regulators
Wonyoung Kim, Meeta Gupta, Gu-Yeon Wei, David Brooks, Harvard University
3 HPCA 2009 
Prediction of CPU Idle-Busy Activity Pattern 
Qian Diao and Justin J Song (Intel Corporation)
4 HPCA 2009 
EXCES: EXternal Caching in Energy Saving Storage Systems (pdf) (slides)
Luis Useche, Jorge Guerra, Medha Bhadkamkar, Mauricio Alarcon, Raju Rangaswami, Florida International University;
5 HPCA 2009 
Performance and Power Optimization through Data Compression in Network-on-Chip Architectures (pdf) (slides)
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulus, Dongkook Park, Vijay Narayanan, Pennsylvania State University;
Ravishankar Iyer, Mazin S. Yousif, Intel Corporation; Chita R Das, Pennsylvania State University;
6 ISCA 2007 
Power Provisioning for a Warehouse-sized Computer
Xiaobo Fan, Wolf-Dietrich Weber, Luiz Andre Barroso, Google Inc.
7 ISCA 2007 
Rotary Router: An Efficient Architecture for CMP Interconnection Networks
Pablo Abad, Valentin Puente, Jose Angel Gregorio, Pablo Prieto, University of Cantabria
8 MICRO 2007 
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas, University of Illinois at Urbana-Champaign
9 MICRO 2007 
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores
Albert Meixner, Michael E. Bauer, Daniel Sorin, Duke University
10 MICRO 2007 
Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0
Naveen Muralimanohar, Rajeev Balasubramonian, University of Utah
Norm Jouppi, HP Labs
11 IEEE MICRO v28-1 (2009) 
Architecting Efficient Interconnects for Large Caches with CACTI 6.0
Naveen Muralimanohar, Rajeev Balasubramonian, University of Utah
Norm Jouppi, HP Labs
12 ISLPED 2007 
Analysis of Dynamic Voltage/Frequency Scaling in Chip-Multiprocessors
S. Herbert and D. Marculescu, Carnegie Mellon University
13 ISLPED 2007 
A Programming Environment with Runtime Energy Characterization for Energy-Aware Applications
C. Xian, Y-H. Lu and Z .Li, Purdue University